1. Field of the Invention
The present invention relates to a fringe field switching type thin film transistor substrate and a fabricating method thereof, and more particularly to a fringe field switching type thin film transistor substrate that is adapted to simplify processing, and a fabricating method thereof.
2. Description of the Related Art
A liquid crystal display (LCD) device controls the light transmittance of liquid crystal by using an electric field to display a picture. Liquid crystal display devices are divided into two main classes according to the electric field direction in which liquid crystal is driven. The classes are vertical electric field applying type liquid crystal display devices and horizontal electric field applying type liquid crystal display devices.
The vertical electric field applying type liquid crystal display device drives a liquid crystal of twisted nematic (hereinafter “TN”) mode by a vertical electric field which is formed between a pixel electrode and a common electrode arranged opposing each other in upper and lower substrates. The vertical electric field applying type liquid crystal display device has an advantage in that its aperture ratio is high but a disadvantage in that its viewing angle is narrow.
The horizontal electric field applying type liquid crystal display device drives a liquid crystal of in-plane switch (hereinafter “IPS”) mode by a horizontal electric field between a pixel electrode and a common electrode which are arranged in parallel in the lower substrate. The horizontal electric field applying type liquid crystal display device has an advantage in that its viewing angle is wide but a disadvantage in that its aperture ratio is low.
In order to improve the above-mentioned disadvantages, there has been proposed a fringe field switching (hereinafter “FFS”) type liquid crystal display device which is operated by a fringe field. The FFS type liquid crystal display device includes a common electrode plate and a pixel electrode, wherein an insulating film is formed therebetween in a pixel area. The FFS type liquid crystal display device also includes a gap between the common electrode plate and the pixel electrode, wherein the gap is formed more narrow than the gap between upper and lower substrates to form a fringe field. The FFS type liquid crystal display device also includes liquid crystal molecules filled between the upper and lower substrates, wherein the liquid crystal molecules are operated by the fringe field, thereby improving aperture ratio and transmittance.
FIG. 1 is a sectional diagram representing a FFS type thin film transistor substrate of the related art;
Referring to FIG. 1, the FFS type thin film transistor substrate of the related art includes a gate line 6 and a data line (not shown) formed on a substrate 20 to cross each other wherein a gate insulating film 22 is formed therebetween; a thin film transistor (hereinafter “TFT”) formed at each crossing of the gate line 6 and the data line; a common electrode plate 14 and a pixel electrode slit 18 which are formed with a gate insulating film 22 and a passivation film 28 therebetween so as to form a fringe field at a pixel area provided by a cross structure of the gate lines 6 and the data line; and a common line 16 connected to the common electrode plate 14.
The common electrode plate 14 is formed at each pixel area and receives a reference voltage (hereinafter “common voltage”) for driving liquid crystal through the common line 16 which is formed on the common electrode plate 14 and connected thereto. The common electrode plate 14 is a transparent conductive layer and the common line 16 is formed of a gate metal layer like the gate line.
The TFT makes a pixel signal of the data line 4 charged and kept in the pixel electrode slit 18 in response to a gate signal of the gate line. For this, the TFT includes a gate electrode 6 connected to the gate line; a source electrode 8 connected to the data line 4; a drain electrode 10 connected to the pixel electrode slit 18; an active layer which overlaps the gate electrode 6 with a gate insulating film 22 therebetween to form a channel between the source electrode 8 and the drain electrode 10; and an ohmic contact layer 26 for having the active layer 24 in ohmic contact with the source electrode 8 and the drain electrode 10. Semiconductor pattern 25 includes contact layer 26 and active layer 24.
The pixel electrode slit 18 is formed to be connected to the drain electrode 10 of the TFT through a contact hole which penetrates the passivation film 28. Also, the pixel electrode slit 18 is formed to overlap the common electrode plate 14. The pixel electrode slit 18 forms a fringe field with the common electrode plate 14 to make liquid crystal molecules, which are arranged in a horizontal direction between a TFT substrate and a color filter substrate, rotate by dielectric anisotropy. The transmittance of the light which penetrates the pixel area is changed in accordance with the extent of rotation of the liquid crystal molecules, thereby realizing the gray level.
Furthermore, there is formed a storage capacitor, which keeps the video signal supplied to the pixel electrode slit 18 stable in an overlapping part of the common electrode plate 14 and the pixel electrode slit 18.
Hereinafter, a fabricating method of a FFS type TFT substrate of the related art is explained, in reference to FIGS. 2A to 2E.
Referring to FIG. 2A, the common electrode plate 14 is formed in each pixel area of the substrate 20 by a first mask process. The common electrode plate 14 is formed at each pixel area by using a first mask to pattern a transparent conductive layer by a photolithography process and an etching process after forming the transparent conductive layer on the substrate 20.
Referring to FIG. 2B, a gate metal pattern inclusive of the gate line, the gate electrode 6 and the common line 16 is formed on the substrate 20 where the common electrode plate 14 is formed by a second mask process. The gate metal pattern is formed by using a second mask to pattern a gate metal layer by the photolithography process and the etching process after forming the gate metal layer on the substrate 20 where the common electrode plate 14 is formed.
Referring to FIG. 2C, the gate insulating film 22 is formed on the substrate 20 where the gate metal pattern is formed. Furthermore, by a third mask process, a semiconductor pattern 25 inclusive of the active layer 24 and the ohmic contact layer 26, and a source/drain metal pattern inclusive of the data line 4, the source electrode 8 and the drain electrode 10 is formed on the gate insulating film 22.
To describe this in detail, the gate insulating film 22, an amorphous silicon layer, n+ amorphous silicon layer and the source/drain metal layer are sequentially formed on the substrate 20 where the gate metal pattern is formed. Then, a photo-resist pattern with a stepped difference is formed by the photolithography process using a third mask, which is a diffractive exposure mask, on the source/drain metal layer. The photo-resist pattern with the stepped difference has relatively low height in a channel part of the TFT. The source/drain pattern and the semiconductor pattern thereunder are formed by the etching process using the photo-resist pattern. Subsequently, the photo-resist pattern is ashed and the exposed source/drain pattern is removed together with the ohmic contact layer 26 thereunder, thereby separating the source electrode 8 and the drain electrode 10.
Referring to FIG. 2D, the passivation film 28 inclusive of the contact hole 12 is formed by a fourth mask process on the gate insulating film 22 where the source/drain metal pattern is formed. The passivation film 28 is formed on the entire surface of the gate insulating film 22 where the source/drain metal pattern is formed and the passivation film 28 is patterned by the photolithography process and the etching process using a fourth mask, thereby forming the contact hole 12 which exposes the drain electrode 10.
Referring to FIG. 2E, the pixel electrode slit 18 is formed on the passivation film 28 by a fifth mask. The pixel electrode slit 18 is formed by using a fifth mask to pattern a transparent conductive layer by the photolithography process and the etching process after forming the transparent conductive layer on the passivation film 28.
In this way, the FFS type TFT substrate of the related art is formed by five mask processes. Each of the mask processes includes many steps such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photo-resist peeling process and an inspection process. Thus, the FFS type TFT substrate of the related art has a disadvantage in that its fabrication is complicated.